java.util.NoSuchElementException: key not found: tbl.T_184.wdata

GitHub | ucbjrl | 2 months ago
  1. 0

    GitHub comment 260#249629939

    GitHub | 2 months ago | ucbjrl
    java.util.NoSuchElementException: key not found: tbl.T_184.wdata
  2. 0

    Exception thrown when running runWithoutDDA on class with clinit methods.

    GitHub | 2 years ago | flankerhqd
    java.util.NoSuchElementException: key not found: Entry@(<clinit>,<clinit>)(envMain,L1)
  3. 0

    key not found: param_Entry:v10@(loadRestriction,loadRestriction)

    GitHub | 2 years ago | maqsoodahmadjan
    java.util.NoSuchElementException: key not found: param_Entry:v10@(loadRestriction,loadRestriction)
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  5. 0

    Exception thrown when running runWithoutDDA on class with clinit methods.

    GitHub | 2 years ago | flankerhqd
    java.util.NoSuchElementException: key not found: Entry@(<clinit>,<clinit>)(envMain,L1)
  6. 0

    scalac 2.11.1 crash in GenASM

    GitHub | 3 years ago | gernst
    java.util.NoSuchElementException: key not found: 5

  1. tyson925 1 times, last 4 months ago
  2. regisso 2 times, last 6 months ago
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Root Cause Analysis

  1. java.util.NoSuchElementException

    key not found: tbl.T_184.wdata

    at scala.collection.MapLike$class.default()
  2. Scala
    HashMap.apply
    1. scala.collection.MapLike$class.default(MapLike.scala:228)
    2. scala.collection.AbstractMap.default(Map.scala:59)
    3. scala.collection.mutable.HashMap.apply(HashMap.scala:65)
    3 frames
  3. firrtl.passes
    VerilogMemDelays$$anonfun$memDelayStmt$3.apply
    1. firrtl.passes.VerilogMemDelays$.firrtl$passes$VerilogMemDelays$$pipe$1(VerilogMemDelays.scala:86)
    2. firrtl.passes.VerilogMemDelays$$anonfun$memDelayStmt$3.apply(VerilogMemDelays.scala:147)
    3. firrtl.passes.VerilogMemDelays$$anonfun$memDelayStmt$3.apply(VerilogMemDelays.scala:140)
    3 frames
  4. Scala
    AbstractTraversable.flatMap
    1. scala.collection.TraversableLike$$anonfun$flatMap$1.apply(TraversableLike.scala:252)
    2. scala.collection.TraversableLike$$anonfun$flatMap$1.apply(TraversableLike.scala:252)
    3. scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
    4. scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
    5. scala.collection.TraversableLike$class.flatMap(TraversableLike.scala:252)
    6. scala.collection.AbstractTraversable.flatMap(Traversable.scala:104)
    6 frames
  5. firrtl.passes
    VerilogMemDelays$$anonfun$1.apply
    1. firrtl.passes.VerilogMemDelays$.memDelayStmt(VerilogMemDelays.scala:140)
    2. firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)
    3. firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)
    3 frames
  6. Scala
    AbstractTraversable.map
    1. scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    2. scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    3. scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
    4. scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
    5. scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
    6. scala.collection.AbstractTraversable.map(Traversable.scala:104)
    6 frames
  7. firrtl.ir
    Block.mapStmt
    1. firrtl.ir.Block.mapStmt(IR.scala:227)
    1 frame
  8. firrtl
    Mappers$StmtMap$.map$extension
    1. firrtl.Mappers$StmtMagnet$$anon$1.map(Mappers.scala:41)
    2. firrtl.Mappers$StmtMap$.map$extension(Mappers.scala:55)
    2 frames
  9. firrtl.passes
    VerilogMemDelays$$anonfun$1.apply
    1. firrtl.passes.VerilogMemDelays$.memDelayStmt(VerilogMemDelays.scala:61)
    2. firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)
    3. firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)
    3 frames
  10. Scala
    List.map
    1. scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    2. scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    3. scala.collection.immutable.List.foreach(List.scala:381)
    4. scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
    5. scala.collection.immutable.List.map(List.scala:285)
    5 frames
  11. firrtl.ir
    Block.mapStmt
    1. firrtl.ir.Block.mapStmt(IR.scala:227)
    1 frame
  12. firrtl
    Mappers$StmtMap$.map$extension
    1. firrtl.Mappers$StmtMagnet$$anon$1.map(Mappers.scala:41)
    2. firrtl.Mappers$StmtMap$.map$extension(Mappers.scala:55)
    2 frames
  13. firrtl.passes
    VerilogMemDelays$$anonfun$memDelayMod$3.apply
    1. firrtl.passes.VerilogMemDelays$.memDelayStmt(VerilogMemDelays.scala:61)
    2. firrtl.passes.VerilogMemDelays$$anonfun$memDelayMod$3.apply(VerilogMemDelays.scala:178)
    3. firrtl.passes.VerilogMemDelays$$anonfun$memDelayMod$3.apply(VerilogMemDelays.scala:178)
    3 frames
  14. firrtl.ir
    Module.mapStmt
    1. firrtl.ir.Module.mapStmt(IR.scala:444)
    1 frame
  15. firrtl
    Mappers$ModuleMap$.map$extension
    1. firrtl.Mappers$ModuleMagnet$$anon$11.map(Mappers.scala:115)
    2. firrtl.Mappers$ModuleMap$.map$extension(Mappers.scala:125)
    2 frames
  16. firrtl.passes
    VerilogMemDelays$$anonfun$6.apply
    1. firrtl.passes.VerilogMemDelays$.memDelayMod(VerilogMemDelays.scala:178)
    2. firrtl.passes.VerilogMemDelays$$anonfun$6.apply(VerilogMemDelays.scala:183)
    3. firrtl.passes.VerilogMemDelays$$anonfun$6.apply(VerilogMemDelays.scala:183)
    3 frames
  17. Scala
    AbstractTraversable.map
    1. scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    2. scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    3. scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
    4. scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
    5. scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
    6. scala.collection.AbstractTraversable.map(Traversable.scala:104)
    6 frames
  18. firrtl.passes
    VerilogMemDelays$.run
    1. firrtl.passes.VerilogMemDelays$.run(VerilogMemDelays.scala:183)
    1 frame
  19. firrtl
    SimpleRun$$anonfun$1.apply
    1. firrtl.SimpleRun$$anonfun$1$$anonfun$2.apply(LoweringCompilers.scala:47)
    2. firrtl.SimpleRun$$anonfun$1$$anonfun$2.apply(LoweringCompilers.scala:47)
    3. firrtl.Utils$.time(Utils.scala:56)
    4. firrtl.SimpleRun$$anonfun$1.apply(LoweringCompilers.scala:47)
    5. firrtl.SimpleRun$$anonfun$1.apply(LoweringCompilers.scala:45)
    5 frames
  20. Scala
    List.foldLeft
    1. scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)
    2. scala.collection.immutable.List.foldLeft(List.scala:84)
    2 frames
  21. firrtl
    Compiler$$anonfun$compile$1.apply
    1. firrtl.SimpleRun$class.run(LoweringCompilers.scala:45)
    2. firrtl.EmitVerilogFromLowFirrtl.run(LoweringCompilers.scala:140)
    3. firrtl.EmitVerilogFromLowFirrtl.execute(LoweringCompilers.scala:156)
    4. firrtl.Compiler$$anonfun$compile$1.apply(Compiler.scala:71)
    5. firrtl.Compiler$$anonfun$compile$1.apply(Compiler.scala:70)
    5 frames
  22. Scala
    List.foldLeft
    1. scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)
    2. scala.collection.immutable.List.foldLeft(List.scala:84)
    2 frames
  23. firrtl
    Driver.main
    1. firrtl.Compiler$class.compile(Compiler.scala:70)
    2. firrtl.VerilogCompiler.compile(LoweringCompilers.scala:201)
    3. firrtl.Driver$.compile(Driver.scala:109)
    4. firrtl.Driver$.run(Driver.scala:183)
    5. firrtl.Driver$.main(Driver.scala:86)
    6. firrtl.Driver.main(Driver.scala)
    6 frames