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via GitHub by ucbjrl
, 1 year ago
key not found: tbl.T_184.wdata
via mail-archive.com by Unknown author, 2 years ago
java.util.NoSuchElementException: key not found: tbl.T_184.wdata	at scala.collection.MapLike$class.default(MapLike.scala:228)	at scala.collection.AbstractMap.default(Map.scala:59)	at scala.collection.mutable.HashMap.apply(HashMap.scala:65)	at firrtl.passes.VerilogMemDelays$.firrtl$passes$VerilogMemDelays$$pipe$1(VerilogMemDelays.scala:86)	at firrtl.passes.VerilogMemDelays$$anonfun$memDelayStmt$3.apply(VerilogMemDelays.scala:147)	at firrtl.passes.VerilogMemDelays$$anonfun$memDelayStmt$3.apply(VerilogMemDelays.scala:140)	at scala.collection.TraversableLike$$anonfun$flatMap$1.apply(TraversableLike.scala:252)	at scala.collection.TraversableLike$$anonfun$flatMap$1.apply(TraversableLike.scala:252)	at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)	at scala.collection.TraversableLike$class.flatMap(TraversableLike.scala:252)	at scala.collection.AbstractTraversable.flatMap(Traversable.scala:104)	at firrtl.passes.VerilogMemDelays$.memDelayStmt(VerilogMemDelays.scala:140)	at firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)	at firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)	at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)	at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)	at scala.collection.AbstractTraversable.map(Traversable.scala:104)	at firrtl.ir.Block.mapStmt(IR.scala:227)	at firrtl.Mappers$StmtMagnet$$anon$1.map(Mappers.scala:41)	at firrtl.Mappers$StmtMap$.map$extension(Mappers.scala:55)	at firrtl.passes.VerilogMemDelays$.memDelayStmt(VerilogMemDelays.scala:61)	at firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)	at firrtl.passes.VerilogMemDelays$$anonfun$1.apply(VerilogMemDelays.scala:61)	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)	at scala.collection.immutable.List.foreach(List.scala:381)	at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)	at scala.collection.immutable.List.map(List.scala:285)	at firrtl.ir.Block.mapStmt(IR.scala:227)	at firrtl.Mappers$StmtMagnet$$anon$1.map(Mappers.scala:41)	at firrtl.Mappers$StmtMap$.map$extension(Mappers.scala:55)	at firrtl.passes.VerilogMemDelays$.memDelayStmt(VerilogMemDelays.scala:61)	at firrtl.passes.VerilogMemDelays$$anonfun$memDelayMod$3.apply(VerilogMemDelays.scala:178)	at firrtl.passes.VerilogMemDelays$$anonfun$memDelayMod$3.apply(VerilogMemDelays.scala:178)	at firrtl.ir.Module.mapStmt(IR.scala:444)	at firrtl.Mappers$ModuleMagnet$$anon$11.map(Mappers.scala:115)	at firrtl.Mappers$ModuleMap$.map$extension(Mappers.scala:125)	at firrtl.passes.VerilogMemDelays$.memDelayMod(VerilogMemDelays.scala:178)	at firrtl.passes.VerilogMemDelays$$anonfun$6.apply(VerilogMemDelays.scala:183)	at firrtl.passes.VerilogMemDelays$$anonfun$6.apply(VerilogMemDelays.scala:183)	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)	at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)	at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)	at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)	at scala.collection.AbstractTraversable.map(Traversable.scala:104)	at firrtl.passes.VerilogMemDelays$.run(VerilogMemDelays.scala:183)	at firrtl.SimpleRun$$anonfun$1$$anonfun$2.apply(LoweringCompilers.scala:47)	at firrtl.SimpleRun$$anonfun$1$$anonfun$2.apply(LoweringCompilers.scala:47)	at firrtl.Utils$.time(Utils.scala:56)	at firrtl.SimpleRun$$anonfun$1.apply(LoweringCompilers.scala:47)	at firrtl.SimpleRun$$anonfun$1.apply(LoweringCompilers.scala:45)	at scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)	at scala.collection.immutable.List.foldLeft(List.scala:84)	at firrtl.SimpleRun$class.run(LoweringCompilers.scala:45)	at firrtl.EmitVerilogFromLowFirrtl.run(LoweringCompilers.scala:140)	at firrtl.EmitVerilogFromLowFirrtl.execute(LoweringCompilers.scala:156)	at firrtl.Compiler$$anonfun$compile$1.apply(Compiler.scala:71)	at firrtl.Compiler$$anonfun$compile$1.apply(Compiler.scala:70)	at scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)	at scala.collection.immutable.List.foldLeft(List.scala:84)	at firrtl.Compiler$class.compile(Compiler.scala:70)	at firrtl.VerilogCompiler.compile(LoweringCompilers.scala:201)	at firrtl.Driver$.compile(Driver.scala:109)	at firrtl.Driver$.run(Driver.scala:183)	at firrtl.Driver$.main(Driver.scala:86)	at firrtl.Driver.main(Driver.scala)